The invention relates to semiconductor device fabrication and, more particularly, to techniques involving siliciding (or, silicidizing) silicon-containing areas in the array region of a dynamic random access memory (DRAM) or embedded DRAM (eDRAM) device to lower electrical resistance and to improve device reliability.
Silicides are alloys of silicon (Si) and metal and are used as contact material in silicon device manufacturing. The various metals which are alloyed with silicon include cobalt (Co, resulting in CoSi2), titanium (Ti, resulting in TiSi2), platinum (Pt, resulting in PtSi), molybdenum (Mo, resulting in MoSi2), tungsten (W, resulting in WSi2), tantalum (Ta, resulting in TaSi2), Nickel (Ni, resulting in NiSi), and Nickel Platinum (NiPt, resulting in NiPtSi).
The one-device DRAM cell consists of a cell transistor with the drain (or source) connected to one node of the cell storage capacitor, the source (or drain) connected to a bit line, and the gate connected to the word line, which runs orthogonal to the bit line. The requirement to have a large capacitor in a small space with low leakage is the main driver of DRAM technology. A brief description of the cell operation will help to explain why. To write, the bit line is driven to a high or low logic level with the cell transistor turned on, and then the cell transistor is shut off, leaving the capacitor charged high or low. Since charge leaks off the capacitor, a maximum refresh interval is specified. To read, or refresh the data in the cell, the bit line is left floating when the cell transistor is turned on, and the small change in bit-line potential is sensed and amplified to a full logic level. The ratio of cell capacitance to bit-line capacitance, called the transfer ratio, which ranges from about 0.1 to 0.2, determines the magnitude of the change in bit-line potential. A large cell capacitance is needed to deliver an adequate signal to the sense amplifier. As further noted in this article, in a folded bit-line configuration, a cell is crossed by two word lines and one bit line. One of the word lines (WL1) is the “active word line” (or simply “word line”) for the cell, and forms the gate of the cell device. The second word line (WL2), the “passing word line,” is the gate of the cell device on the adjacent cell.
U.S. Pat. No. 6,410,399 (referred to as “the '399 patent”) discloses a process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization. As disclosed therein, insofar as eDRAMs are concerned, the buried strap is a conductive pathway in an eDRAM device located between the active silicon on the drain side of the field effect transistor (FET) and the trench capacitor. The buried strap facilitates charges to be written to, or read from, the capacitor and comprises a highly doped portion of the substrate. Physically, the buried strap is approximately 100 nm thick, extends across the pathway, and is buried approximately 50 nm below the surface of the substrate.
As noted in the '399 patent, in the art, it is known to use various approaches to reduce resistance and improve reliability at lower temperatures. For example, designers have implemented shorter pathways in conjunction with utilizing highly conductive metals, and/or highly doped areas of the substrate, and/or highly conducting silicides, notably, the silicides of cobalt, nickel and titanium.
As noted in the '399 patent, in this regard, silicides are conventionally formed in self-aligned processes, whereby a metal film is deposited over the silicon-containing region to be silicidized (silicided). The process involves in-situ cleaning of the silicon-containing region, followed by deposition of a metal on the silicon-containing region by means well known in the art. Thereafter, the structure is annealed by heating to form the silicide. Any unreacted metal that is not silicided may be removed by a selective wet etching process to remove metal without attacking the silicide. In DRAM and eDRAM devices, silicides may be found in the drain region, bitline contact, wordline and interconnecting pathways.
As noted in the '399 patent, in the art, silicidizing (siliciding) silicon-containing regions has achieved success in reducing resistance and improving functionality at low operating temperatures, however, notwithstanding the success, it has become evident that DRAM yields are affected by: a) excessive node junction leakage due to the presence of the silicide; and b) silicide agglomeration on the wordline and in the active area. As a result, current DRAM and eDRAM manufacturing processes have steered completely away from silicidizing the pathways and structures. Consequently, the only silicide seen is these structures is a polycided wordline i.e., gate conductor (GC), comprising tungsten silicide on a highly doped polysilicon.
As noted in the '399 patent, since silicides offer the potential for low resistance and reliable operation at low temperature, it is desirable to continue to utilize silicides in memory structures, but without the aforementioned problems.
FIG. 1 illustrates, generally, a DRAM (or eDRAM) cell 100 based on the teachings of the '399 patent. The description is very general, and is intended to give the reader a sense of what is going on technically, as well as a sense of scale. Dimensions are merely exemplary. The processes required to form the various structures are all very well known to those having ordinary skill in the art to which the present invention most nearly pertains, and therefore need not be discussed in any great detail.
An exemplary one of a plurality of DRAM cells 100 is disposed adjacent an exemplary one of a plurality of logic devices (not shown) in a silicon (Si) substrate (wafer) 102. The silicon wafer 102 may be lightly doped. For each DRAM cell, a deep trench (DT) 104 is formed in the wafer 102, extending from the top surface of the wafer into the substrate 102. Preferably, the trench 104 has an aspect ratio (depth:width) of greater than 40:1. A typical trench for a DRAM cell would have depth (vertical on the page) of approximately greater than 60,000 Angstroms (6000 nm, 6 μm), a width (across the page) of approximately greater than 1000 Angstroms (>100 nm, >0.1 μm), and a length (into the page) of approximately greater than 1500 Angstroms (>150 nm, >0.15 μm), and an overall elliptical cylinder type.
A cell capacitor 110 is formed at a bottom portion of the deep trench 104 and comprises (electrically speaking) a first plate 112, a second plate 114, and a dielectric (node dielectric) 116 separating the two plates. The first plate 112, sometimes referred to as the “buried plate”, is simply a heavily doped region in the substrate 102 adjacent a bottom portion of the trench 104. The second plate 114 (sometimes referred to as “node plate”) is a conductive structure which is formed in the bottom of the trench, such as n+ (arsenic doped) polysilicon. The node dielectric 116 is suitably nitride or oxynitride formed in the bottom portion of the trench. The height of the cell capacitor 110 is typically approximately greater than 4.5 μm (micrometer), and it typically has a capacitance of approximately 20-40 fF (femtoFarads).
A storage node conductor (or simply, “node”) 106 extends from near the top of the trench 104 to the node plate 114 of the cell capacitor 110, and is surrounded by a collar 108 of oxide. (Or, looking at it in the other direction, the node conductor extends from the cell capacitor, through the collar, towards the top of the trench.) The collar 108 is disposed above the cell capacitor 110 in the deep trench 104. The storage node conductor 106 comprises n+ polysilicon, has a length of >1 μm, and has a thickness of >40 nm. The collar 108 comprises oxide, has a length of approximately 0.7 μm, and has a thickness of >30 nm. Generally speaking, the storage node conductor 106 connects the cell capacitor 110 to a cell transistor (120), as described in greater detail hereinbelow.
A cell transistor 120 is associated with and connected to the cell capacitor 110. A buried strap (not specifically shown, usually arsenic (As) dopant in the node conductor 106) is disposed atop the collar 108 and out-diffuses (to the left in the figure) to become a doped (n−) node 122 (i.e., the source, or drain, of the cell transistor 120, depending on polarity, hereinafter “source diffusion”) of the cell transistor 120. A polysilicon (poly) conductor (PC) 124 is disposed atop a thin gate oxide 126 on the surface of the substrate 102, adjacent but spaced from the trench 104. The PC 124 functions as the gate conductor (GC) of the cell transistor 120, and also functions as the “word line” (WL) of the DRAM cell. The source diffusion region 122 extends from the trench 104, namely from the node conductor 106, to just under the PC 124. Another diffusion area (n−) 128 is formed on the other side of the PC 124, and will serve as the drain (or source, of the cell transistor 120, depending on polarity) of the cell transistor 120.
FIG. 1A illustrates an equivalent circuit for the DRAM cell described hereinabove. A cell transistor is represented having a source (S) connected via the node conductor (106) to the node plate (114), a drain (D) typically connected to a bit line (not shown), and a gate (G) connected to a word line (not shown). Generally, the source (S) can be swapped for the drain (D), depending on the chosen polarity of the overall circuit.
Returning to FIG. 1, oxide comprising trench top oxide (TTO) 131 and shallow trench isolation (STI) 130 is disposed in a top portion of the trench 104, generally atop the collar 108, and level with the top surface of the substrate 102. The TTO 131 is an oxide structure on top of the DT node 106, for isolating electrically DT node 106 and passing word line (PWL) 134. The STI 130 is an oxide structure, for isolating electrically between adjacent DRAM cells. (For example, a second DRAM cell (not shown) which is a mirror image of the illustrated DRAM cell, disposed adjacent, immediately to the right of the DRAM cell which is shown. The STI would extend into both DTs, separating and isolating the two DTs from one another.) Generally, the TTO 131 is formed first by depositing oxide on top of DT node 106, and then followed by STI litho (lithography) and RIE (reactive ion etching). Oxide is deposited to fill the etched region and it forms the STI 130, followed by STI CMP (Chemical Mechanical Polish). STI RIE will etch the deep trench (DT) 104, collar oxide 108 and Si substrate 102 simultaneously. The general purpose of the STI structure 130 is to isolate both DRAM cells and logic devices. Therefore the STI process is typically executed at both DRAM array and logic device region simultaneously.
A second PC line 134 (compare 124) is formed atop the TTO 131 and the STI oxide 130, generally above the trench 104, and functions as a “passing word line” (PWL).
A third PC line 144 (compare 124) is shown, formed atop thin gate oxide 126 on the surface of the substrate 102, on a far end of the drain diffusion 128, and would function as a word line for another DRAM cell adjacent (again “mirror” image, this time to the left of) the illustrated DRAM cell.
The three PC lines 124 (as shown cell), 134 (back or front cell of STI 130) and 144 (left hand side DRAM cell of CA contact 136) all function as gate electrodes (or gate conductors (GCs)) at different cells. The GC 144 is essentially a “mirror image” of the GC 124—the CA contact 136 acting as a kind of “pivot point”.
Sidewall spacers 125, 135 and 145 are formed in a conventional manner on both sides of the respective gate electrodes 124, 134 and 144, as illustrated. The gate electrodes 124, 134 and 144 are typically similarly sized (substantially the same size as one another), having a width (left-to-right, as viewed) such as approximately 90 nm (which is according to “design rule”, in this example the design rule is 90 nm). The sidewall spacers 125, 135 and 145 typically all have the same thickness (“t”, which is the thickness of the sidewall spacer deposition), such as approximately 30-50 nm. The sidewall spacers 125, 135 and 145 suitably comprise nitride. In this example, the thickness of each of the sidewall spacers is approximately 30-40 nm.
The gate electrodes 124, 134 and 144 are shown as being evenly spaced from one another. (Evenly spaced gate electrodes have benefit in litho and RIE.) There is a space (X) between adjacent gate electrodes, such as approximately 90-100 nm. This space (X) between adjacent gate electrodes is greater than twice (2×) the thickness (t) of a given sidewall spacer (X>2t). The importance of these dimensions and their relationship to one another will become more apparent from the description of FIG. 2 that follows.
After sidewall spacer formation, the structure is silicided. This results in silicide being formed everywhere that silicon (or polysilicon) is exposed. (Silicide does not form on materials such as nitride or oxide.) More particularly, silicide 127, 137 and 147 is formed on the exposed top surfaces of the respective gate electrodes 124, 134 and 144, as illustrated. This is common procedure, and the silicide is very beneficial as a contact material. The silicide 127, 137, 147 atop poly 124, 134, 144 typically has a thickness of 30-40 nm.
During silicidization (silicidation), silicide is also formed on exposed areas of the substrate 102, whether doped or not. In one instance, silicide 107 is formed on the drain region 128 in the exposed area between the sidewall spacers 145 and 125. A CA (Contact Array) contact 136 extends through interlevel dielectric (ILD) 138 to make contact with the drain 128, via the silicide 107. This is common procedure, and the silicide 107 is very beneficial as a contact material. The silicide 107 atop silicon has a thickness of approximately 30 nm. (The CA contact 136 will function as the aforementioned “bit line” (BL) contact.)
It should be noted that there is a gap between the sidewall spacers 125 (on the right hand side of gate electrode 124) and 135 (on the left hand side of gate electrode 134). Part of this gap comprises exposed substrate surface in the source (S) diffusion area 122, and part of the gap comprises exposed TTO (oxide) 131. During silicidization (silicidation), silicide 109 will form on the exposed surface of the diffusion area 122. This is common procedure, but the silicide is not beneficial in this area because (i) it is not serving any useful purpose as a contact material, and (ii) it creates a severe electric potential gradient that adversely affects retention time.
It will of course be understood that DRAM cells need power supply, voltage amplifier, ring oscillator, etc. All these devices are logic devices and are located in a support region near the DRAM cells. These devices are omitted, for illustrative clarity. Although included in the drawing, the elements to the left of the CA contact are really not necessary for understanding the context or principles of the invention (described hereinbelow).
For purposes of this discussion, the main problem being illustrated by FIG. 1 is that silicide 109 is formed within what is called the “memory cell area” of the DRAM cell—more particularly, right in the source region 122 of the DRAM cell itself, rather than only on the PC lines or on the drain contact (128) which is considered to be outside of the memory cell area since it is on the other (far) side of the gate (word line) 124.
FIG. 2 illustrates a prior art solution to the problem of silicide forming in the memory cell area of the DRAM cell 200. This solution is proposed by “New Embedded DRAM Technology using Self-aligned Salicide (Self-Aligned Silicide) Block (SSB) Process for 0.18 um SOC (System on a Chip)”, Kokubun et al, ULSI Device Engineering Laboratory, Semiconductor Group, Toshiba Corporation. As noted in the article,
The embedded DRAM (eDRAM) is one of the key device to meet the demand for a system on a single chip. The best way to realize high performance eDRAM is to introduce Logic technology directly, such as dual work function gate and salicide technology. However, it was reported that applying salicide technology directly to trench capacitor DRAM memory cell area degraded DRAM retention characteristics because of junction leak of silicided storage node contact in array.
The DRAM cell of FIG. 2 is very similar to that of FIG. 1, and therefore identical elements will be labeled identically. Similar elements will generally be labeled similarly (e.g., gate electrode 224 is similar but not identical to gate electrode 124.) The difference, generally, is that what is being done in FIG. 2 versus FIG. 1 is that the word line (WL) 224 (compare 124, FIG. 1) is moved closer to the passing word line (PWL) 234 (compare 134, FIG. 1) so that there is no gap between the respective adjacent sidewall spacers (225 and 235)—hence, there is no exposed silicon in the source diffusion area 222 (compare 122) that can become silicided (109), therefore performance is not degraded. Also, due to the similarities between FIG. 2 and FIG. 1, lower structures such as the cell capacitor (110) are not shown, for illustrative clarity, the figure terminating in the middle of the collar 108. Also, the upper portion of the CA contact 236 (compare 136) and the ILD (compare 138) are not explicitly shown, again for illustrative clarity.
Generally, in this example, the GC (word line) 224 is moved further from the CA 236, to get closer to the GC (passing word line) 234 and, in this example, the sidewall spacers “merge” and there is no gap between them as there was in the example of FIG. 1.
Since the word line 224 is further from the CA contact 236, the “mirror image” word line of the adjacent (to the left) cell is also a bit further from the CA contact 236. This is illustrative of the fact that it is convenient to use the CA contact as a “pivot point” (reference point) in the design.
More particularly, the DRAM cell comprises a deep trench 104. A collar 108 is disposed in the trench atop the cell capacitor (110, not shown). Trench Top Oxide (TTO) 131 and shallow trench oxide (STI) 130 is formed at an upper portion of the trench, and has a top surface substantially even with the top surface of the substrate 102.
A cell transistor 220 (compare 120) is associated with and connected to the cell capacitor (110). A buried strap is disposed atop the collar 108 and out-diffuses (to the left in the figure) to the source (S) region 222 (compare 122) of the cell transistor 220. A PC line 224 (compare 124) is disposed atop a thin gate oxide 226 (compare 126) on the surface of the substrate 102, adjacent but spaced from the trench 104. The PC line 224 functions as the gate (G) of the cell transistor, and also functions as the “word line” of the DRAM cell. The source (S) diffusion 222 extends from the trench 104, namely from the node conductor 106, to just under the PC line 224. Another diffusion area (n−) 228 (compare 128) is formed on the other side of the PC line 224, and will serve as the drain (or source, of the cell transistor 220, depending on polarity) of the cell transistor 220. The equivalent circuit of the memory cell of FIG. 2 is essentially the same as the equivalent circuit of the memory cell of FIG. 1. (See FIG. 1A.)
The source diffusion 222 looks a little different than the source diffusion 122, and this is because it is slightly narrower, due to the narrower spacing between GCs 224 and 234.
A second PC line (gate electrode) 234 (compare 124) is formed atop the TTO 131 and the STI oxide 130 generally atop the trench 104, and functions as a “passing word line” (PWL).
A third PC line (gate electrode) 244 (compare 124) is formed atop thin gate oxide 126 on the surface of the substrate 102, on a far end of the drain diffusion 128, and functions as a word line for an adjacent DRAM cell, as described above.
Sidewall spacers 225, 235 and 245 (compare 125, 135 and 145) are formed on sides of the respective gate electrodes 224, 234 and 244, as illustrated. The sidewall spacers have a width (thickness “t”) of approximately 30-40 nm, as was the case in FIG. 1.
The gate electrodes 224, 234, 244 are typically similarly sized (substantially the same size as one another), having a width (left-to-right, as viewed) of approximately the size of design rule, as was the case in FIG. 1. However, whereas in FIG. 1 the gate electrodes 124, 134 and 144 were shown as being evenly spaced from one another (X˜ the size of design rule), in this case the PC lines 224, 234, 244 are not evenly spaced from one another. Notably, the gate electrodes 224 (word line) and 234 (passing word line) are much closer to one another in FIG. 2 than they were in FIG. 1. For example, there is a space of approximately 40-70 nm (90 nm of design rule), between adjacent the gate electrodes 244 and 224, and there is a space of approximately 110-140 nm (90 nm of design rule), between the adjacent gate electrodes 224 and 234. This latter dimension is the important thing that is being illustrated here. Generally, the scale of the two figures (FIGS. 1 and 2) are the same as one another, although no representation is made here that they are truly to scale.
Because the sidewall spacers have a thickness (t) greater than half the distance between the word line 224 and the passing word line 234, the material (e.g., nitride) of the sidewall spacer will fill the gap between the PC lines 224 and 234, and therefore there is no exposed silicon in the source diffusion area 222 (compare 122) that can become silicided (109), hence memory cell performance is not degraded.
After sidewall spacer formation, the structure is silicided, as described above. This results in silicide structures 227, 237 and 247 (compare 127, 137 and 147) is formed on the exposed top surfaces of the respective PC lines 224, 234 and 244.
Silicide is also formed on exposed areas of the substrate, such as in the exposed area 207 between the sidewall spacers 245 and 225. A CA contact 236 (compare 136) extends through interlevel dielectric (ILD, 110, not explicitly shown) to make contact with the drain 228, via the silicide 207.
Because there is no gap between the sidewall spacers 225 and 235, during silicidization (silicidation), silicide will not form on the diffusion area 222. Therefore, a severe electric potential gradient (as discussed above, with respect to FIG. 1) will not be created that adversely affects retention time. However, the problem with the FIG. 2 solution is with GC litho and RIE. Un-even spacing of the gate electrodes (GCs) makes it difficult to pattern the GC line and it caused difficulty in shrinking the devices. GC RIE also has problem in etching the GC line. At the very narrow region, RIE tends to be very difficult.
From the above it becomes apparent that there is an ongoing need to lower wordline resistance and bitline contact resistance, improve retention time while advantageously employing array silicide, and to improve the margin of gate conductor (GC) lithography.